Our Services
SoC
- SoC floorplanning; IO ring construction
- ESD protection strategy
- ESD protection strategy
- 3rd party IP integration; Analogue IP integration
- Power network design and analysis
- Digital Place & Route (Synopsys & Cadence flows)
- Clock Tree Synthesis (CTS); Timing closure
- Timing signoff (PrimeTime STA)
- Layout verification (Calibre & Assura)
Full-custom Design
- IO design & layout
- ESD protection circuitry design, simulation and layout
- Amplifier design and layout
- RF/Analogue layout
- Chip floorplanning
- Power network design and analysis
- Analogue Design for Test (DfT) strategy development
- Package development
- Behavioural modelling and verification
- ESD protection circuitry design, simulation and layout
- Amplifier design and layout
- RF/Analogue layout
- Chip floorplanning
- Power network design and analysis
- Analogue Design for Test (DfT) strategy development
- Package development
- Behavioural modelling and verification
Project Management
- CAD flow development
- Project Management
- Project Management